Chapter 9 POWER MODELING AND REDUCTION OF VLIW PROCESSORS

Power is rapidly becoming one of the primary design constraints for modern processor design due to increased complexity and speed of the system. Cycle-accurate microarchitecture-level power simulators such as Wattch [1], SimplePower [2], and TE EST [3], have been developed and used extensively to validate power-efficient microarchitecture innovations, including clock gating [4], dynamically reconfiguring resources [5], etc. However, all aforementioned work focuses on superscalar architecture. In this chapter, we study power modeling and reduction for VLIW architectures. Our contributions include: